In recent years, a ReRAM (Resistive Random Access Memory) which stores resistance value information, for a high resistance state and a low resistance state of an electrically rewritable variable resistive element in a non-volatile manner has drawn attention as a non-volatile memory device. In a memory cell array region of the ReRAM, for example, variable resistance memory cells in which includes variable resistive elements as memory elements and rectifying elements such as diode which is connected in series to the variable resistive elements are arranged at intersection portions of a plurality of word lines extending parallel to each other in a first direction and a plurality of bit lines extending parallel to each other in a second direction perpendicular to the first direction in an array shape. The word line and the bit line are extracted to a word line hookup region and a bit line hookup region, respectively, to be connected through contacts to different wiring layers.
In the word line hookup region and the bit line hookup region, contact connection portions for connecting the contacts to each of the word lines and each of the bit lines are formed so that the formation positions do not overlap between adjacent wirings. As a result, word line wiring lengths or bit line wiring lengths for matching the memory cell array region and the hookup regions are different between adjacent wirings. Therefore, in a stage of processing word lines or bit lines by using a dry etching process, a phenomenon occurs where charge-up amounts of wirings are different. Particularly, in a cross point type memory, after an upper-layer wiring is processed, a memory cell at an intersection point needs to be subsequently processed. However, in the state where the upper-layer wiring is processed, the charge-up amounts are different between the wirings. If an interlayer insulating film embedded between the memory cells is processed by dry etching in this state, there are problems in that dimensional defect occurs in the side etching of the upper-layer wiring caused by a curved trajectory of incident particles (ions, electrons) or in that falling and short-circuit of the upper-layer wiring occurs due to the side etching of the interlayer insulating film under the upper-layer wiring.